1. Field of the Invention
The present invention generally relates to field effect transistor (FET) circuits having particular application to integrated circuit technology, and more specifically to an FET load gate compensator which will hold the circuit delay and power dissipation of an integrated circuit chip nearly constant.
2. Description of the Prior Art
In integrated circuits employing FETs there are several parameters which, while fixed in a particular integrated circuit chip, may vary from integrated circuit chip to chip due to manufacturing tolerances. These include the transconductance (.gamma..sub.m) of the FETs, the threshold voltage (V.sub.T) of the FETs, the device width and length of the FETs, and the capacitive leadings of the interconnections. Besides these on-chip parameters, there are external variables such as temperature, and supply voltages, which may vary from application to application or within a specific application of the integrated circuits. The variation in on-chip parameters and the external variables associated with a particular application of the integrated circuit all contribute to variations in circuit delay and power dissipation of the integrated circuit chips. This complicates design requiring delay calculations and race condition considerations. Furthermore, input noise immunity is degraded because of the relationship of circuit delay and power dissipation due to variations in supply voltages. While it is known to provide a source of regulated supply voltage to overcome in part these problems, such regulated voltage supplies are complicated and employ Zener diodes. Such regulated voltage supplies cannot compensate for variations in on-chip parameters.